/*
 * Copyright (C) 2017 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 */

/* This file is generated by GenLP_setting.pl v1.5.7 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>

const unsigned int AP_DCM_Golden_Setting_tcl_gs_dpidle_data[] = {
/*      Address     Mask        Golden Setting Value */
	0x10001070, 0x40F07FFF, 0x40F00603,/* INFRA_BUS_DCM_CTRL */
	0x10001074, 0xBFFFFFFB, 0xB07F83E3,/* PERI_BUS_DCM_CTRL */
	0x10001078, 0xBFFF01C1, 0x0BE00180,/* MEM_DCM_CTRL */
	0x1000107C, 0x07FF01C1, 0x03E00180,/* DFS_MEM_DCM_CTRL */
	0x100010A0, 0x0000000F, 0x00000000,/* P2P_RX_CLK_ON */
	0x10001F00, 0x10000000, 0x10000000,/* INFRA_MISC */
	0x1001A208, 0x0000FFFF, 0x00000000,/* DXCC_NEW_HWDCM_CFG */
	0x10200088, 0x00000001, 0x00000001,/* MP0_RGU_DCM_CONFIG */
	0x10200288, 0x00000001, 0x00000001,/* MP1_RGU_DCM_CONFIG */
	0x10200648, 0x00000001, 0x00000001,/* L2C_SRAM_CTRL */
	0x10200660, 0x00000100, 0x00000100,/* CCI_status */
	0x10200668, 0x3FFF1FFF, 0x3FFF1FFF,/* mcusys_bus_fabric_dcm_ctrl */
	0x1020066C, 0x00000003, 0x00000003,/* mcu_misc_dcm_ctrl */
	0x10200740, 0x0000087F, 0x0000087F,/* MP_CCI_ADB400_DCM_CONFIG */
	0x10200744, 0x00100401, 0x00100401,/* MP_SYNC_DCM_CONFIG */
	0x1020074C, 0x00009F9F, 0x00008C8C,/* MP_SYNC_DCM_CLUSTER_CONFIG */
	0x10200758, 0x00000001, 0x00000001,/* gic_sync_dcm */
	0x102007A0, 0x80000800, 0x80000800,/* mp0_pll_divider_cfg */
	0x102007A4, 0x80000800, 0x80000800,/* mp1_pll_divider_cfg */
	0x102007C0, 0x00000800, 0x00000800,/* bus_pll_divider_cfg */
	0x10200B60, 0xFFFF0000, 0xFFFF0000,/* MCSIA_DCM_EN */
	0x10228284, 0x000BFF00, 0x00000000,/* MISC_CG_CTRL0 */
	0x1022828C, 0x07E000C0, 0x01000000,/* MISC_CG_CTRL2 */
	0x102282A8, 0x0C000000, 0x00000000,/* MISC_CTRL3 */
	0x1022A038, 0xC4000007, 0xC0000007,/* DRAMC_PD_CTRL */
	0x1022A03C, 0x80000000, 0x80000000,/* CLKAR */
	0x1022D008, 0xFF000000, 0x00000000,/* CHN_EMI_CONB */
	0x10230284, 0x000BFF00, 0x00000000,/* MISC_CG_CTRL0 */
	0x1023028C, 0x07E000C0, 0x01000000,/* MISC_CG_CTRL2 */
	0x102302A8, 0x0C000000, 0x00000000,/* MISC_CTRL3 */
	0x10232038, 0xC4000007, 0xC0000007,/* DRAMC_PD_CTRL */
	0x1023203C, 0x80000000, 0x80000000,/* CLKAR */
	0x10235008, 0xFF000000, 0x00000000,/* CHN_EMI_CONB */
	0x11220000, 0x60000000, 0x60000000,/* AUDIO_TOP_CON0 */
	0x11C50480, 0x00000007, 0x00000007,/* DCM_ON */
	0x13FFE010, 0x80008000, 0x00000000,/* MFG_DCM_CON_0 */
	0x14000120, 0x3FFFFFFF, 0x00000000,/* MMSYS_HW_DCM_1ST_DIS0 */
	0x14000130, 0x0003FFFF, 0x00000000,/* MMSYS_HW_DCM_2ND_DIS0 */
	0x14002300, 0x000000FE, 0x00000000,/* SMI_DCM */
	0x14003014, 0x0000FFF0, 0x0000FFF0,/* SMI_LARB_CON_SET */
	0x15021014, 0x0000FFF0, 0x0000FFF0,/* SMI_LARB_CON_SET */
	0x17010014, 0x0000FFF0, 0x0000FFF0,/* SMI_LARB_CON_SET */
	0x17030300, 0x00000001, 0x00000000,/* JPGENC_DCM_CTRL */
	0x1A002014, 0x0000FFF0, 0x0000FFF0,/* SMI_LARB_CON_SET */
};

const unsigned int *AP_DCM_Golden_Setting_tcl_gs_dpidle =
		AP_DCM_Golden_Setting_tcl_gs_dpidle_data;

unsigned int AP_DCM_Golden_Setting_tcl_gs_dpidle_len = 132;

const unsigned int AP_DCM_Golden_Setting_tcl_gs_suspend_data[] = {
/*      Address     Mask        Golden Setting Value */
	0x10001070, 0x40F07FFF, 0x40F00603,/* INFRA_BUS_DCM_CTRL */
	0x10001074, 0xBFFFFFFB, 0xB07F83E3,/* PERI_BUS_DCM_CTRL */
	0x10001078, 0xBFFF01C1, 0x0BE00180,/* MEM_DCM_CTRL */
	0x1000107C, 0x07FF01C1, 0x03E00180,/* DFS_MEM_DCM_CTRL */
	0x100010A0, 0x0000000F, 0x00000000,/* P2P_RX_CLK_ON */
	0x10001F00, 0x10000000, 0x10000000,/* INFRA_MISC */
	0x1001A208, 0x0000FFFF, 0x00000000,/* DXCC_NEW_HWDCM_CFG */
	0x10200088, 0x00000001, 0x00000001,/* MP0_RGU_DCM_CONFIG */
	0x10200288, 0x00000001, 0x00000001,/* MP1_RGU_DCM_CONFIG */
	0x10200648, 0x00000001, 0x00000001,/* L2C_SRAM_CTRL */
	0x10200660, 0x00000100, 0x00000100,/* CCI_status */
	0x10200668, 0x3FFF1FFF, 0x3FFF1FFF,/* mcusys_bus_fabric_dcm_ctrl */
	0x1020066C, 0x00000003, 0x00000003,/* mcu_misc_dcm_ctrl */
	0x10200740, 0x0000087F, 0x0000087F,/* MP_CCI_ADB400_DCM_CONFIG */
	0x10200744, 0x00100401, 0x00100401,/* MP_SYNC_DCM_CONFIG */
	0x1020074C, 0x00009F9F, 0x00008C8C,/* MP_SYNC_DCM_CLUSTER_CONFIG */
	0x10200758, 0x00000001, 0x00000001,/* gic_sync_dcm */
	0x102007A0, 0x80000800, 0x80000800,/* mp0_pll_divider_cfg */
	0x102007A4, 0x80000800, 0x80000800,/* mp1_pll_divider_cfg */
	0x102007C0, 0x00000800, 0x00000800,/* bus_pll_divider_cfg */
	0x10200B60, 0xFFFF0000, 0xFFFF0000,/* MCSIA_DCM_EN */
	0x10228284, 0x000BFF00, 0x00000000,/* MISC_CG_CTRL0 */
	0x1022828C, 0x07E000C0, 0x01000000,/* MISC_CG_CTRL2 */
	0x102282A8, 0x0C000000, 0x00000000,/* MISC_CTRL3 */
	0x1022A038, 0xC4000007, 0xC0000007,/* DRAMC_PD_CTRL */
	0x1022A03C, 0x80000000, 0x80000000,/* CLKAR */
	0x1022D008, 0xFF000000, 0x00000000,/* CHN_EMI_CONB */
	0x10230284, 0x000BFF00, 0x00000000,/* MISC_CG_CTRL0 */
	0x1023028C, 0x07E000C0, 0x01000000,/* MISC_CG_CTRL2 */
	0x102302A8, 0x0C000000, 0x00000000,/* MISC_CTRL3 */
	0x10232038, 0xC4000007, 0xC0000007,/* DRAMC_PD_CTRL */
	0x1023203C, 0x80000000, 0x80000000,/* CLKAR */
	0x10235008, 0xFF000000, 0x00000000,/* CHN_EMI_CONB */
	0x11220000, 0x60000000, 0x60000000,/* AUDIO_TOP_CON0 */
	0x11C50480, 0x00000007, 0x00000007,/* DCM_ON */
	0x13FFE010, 0x80008000, 0x00000000,/* MFG_DCM_CON_0 */
	0x14000120, 0x3FFFFFFF, 0x00000000,/* MMSYS_HW_DCM_1ST_DIS0 */
	0x14000130, 0x0003FFFF, 0x00000000,/* MMSYS_HW_DCM_2ND_DIS0 */
	0x14002300, 0x000000FE, 0x00000000,/* SMI_DCM */
	0x14003014, 0x0000FFF0, 0x0000FFF0,/* SMI_LARB_CON_SET */
	0x15021014, 0x0000FFF0, 0x0000FFF0,/* SMI_LARB_CON_SET */
	0x17010014, 0x0000FFF0, 0x0000FFF0,/* SMI_LARB_CON_SET */
	0x170200F4, 0x00000001, 0x00000001,/* VENC_CLK_DCM_CTRL */
	0x17020130, 0xFFFFFFFF, 0xFFFFFFFF,/* VENC_CLK_CG_CTRL */
	0x17030300, 0x00000001, 0x00000000,/* JPGENC_DCM_CTRL */
	0x1A002014, 0x0000FFF0, 0x0000FFF0,/* SMI_LARB_CON_SET */
};

const unsigned int *AP_DCM_Golden_Setting_tcl_gs_suspend =
		AP_DCM_Golden_Setting_tcl_gs_suspend_data;

unsigned int AP_DCM_Golden_Setting_tcl_gs_suspend_len = 138;

const unsigned int AP_DCM_Golden_Setting_tcl_gs_sodi_data[] = {
/*      Address     Mask        Golden Setting Value */
	0x1001A208, 0x0000FFFF, 0x00000000,/* DXCC_NEW_HWDCM_CFG */
	0x10228284, 0x000BFF00, 0x00000000,/* MISC_CG_CTRL0 */
	0x1022828C, 0x07E000C0, 0x01000000,/* MISC_CG_CTRL2 */
	0x102282A8, 0x0C000000, 0x00000000,/* MISC_CTRL3 */
	0x10230284, 0x000BFF00, 0x00000000,/* MISC_CG_CTRL0 */
	0x1023028C, 0x07E000C0, 0x01000000,/* MISC_CG_CTRL2 */
	0x102302A8, 0x0C000000, 0x00000000,/* MISC_CTRL3 */
	0x11C50480, 0x00000007, 0x00000007,/* DCM_ON */
	0x14000120, 0x3FFFFFFF, 0x00000000,/* MMSYS_HW_DCM_1ST_DIS0 */
	0x14000130, 0x0003FFFF, 0x00000000,/* MMSYS_HW_DCM_2ND_DIS0 */
	0x17030300, 0x00000001, 0x00000000,/* JPGENC_DCM_CTRL */
};

const unsigned int *AP_DCM_Golden_Setting_tcl_gs_sodi =
		AP_DCM_Golden_Setting_tcl_gs_sodi_data;

unsigned int AP_DCM_Golden_Setting_tcl_gs_sodi_len = 33;

